As advancements have enabled ICs to perform circuit operations at greater and greater speeds, ICs have become more sensitive to the inductances of the bond wires, IC package leads, and external supply lines that provide operating power. The effects of these parasitic inductances must be suitably controlled in order to avoid undesired modes of circuit operation.
An understanding of the way in which these inductances affect circuit performance is facilitated with the assistance of FIG. 1 which illustrates a cross-section of a typical dual-in-line packaged IC. The central portion of this packaged IC is a semiconductor die 10 consisting of a generally flat monocrystalline silicon semiconductive body 12 and an adjoining electrical interconnection system 14. Semiconductive body 12 is divided into various P-type and N-type semiconductive regions (not shown). Interconnection system 14 is divided into various electrically conductive and electrically insulating regions of which FIG. 1 only depicts internal power supply lines 16.sub.L and 16.sub.H. The semiconductive regions in body 12 together with the electrical interconnections provided by system 14 define a group of electronic circuitry elements. Lines 16.sub.L and 16.sub.H (usually consisting principally of a metal such as aluminum) transmit internal supply voltages that provide power to operate the circuitry elements.
Die 10 is mounted on a metal leadframe 18 along a thin electrically insulating layer 20 formed along the bottom of body 12. An electrically insulating package 22 (typically fabricated with a thermosetting resin or a ceramic material) substantially surrounds die 10 (and leadframe 18) to protect die 10. A set of metallic electrical conductors extend through package 22 to contact bond pads in interconnection system 14. Each of these conductors consists of an externally protruding electrical lead and a bond wire that extends between the lead and the associated bond pad. As indicated in FIG. 1, bond wires 24.sub.L and 24.sub.H thus respectively connect externally accessible supply leads 26.sub.L and 26.sub.H with supply lines 16.sub.L and 16.sub.H.
FIG. 2 is a circuit diagram which generally illustrates the major inductances that affect the operation of the IC in FIG. 1. Dashed lines 10 and 22 in FIG. 2 respectively represent the physical extents of die 10 and package 22 in FIG. 1. Leads 26.sub.L and 26.sub.H are represented as pins (or terminals) in FIG. 2. The circuitry elements in die 10 are generally denoted by block 28 that L receives internal high and low supply voltages V.sub.HHD and V.sub.LLD along respective lines 16.sub.H and 16.sub.L. Item L.sub.HP is the parasitic inductance associated with wire 24.sub.H and lead 26.sub.H. Similarly, item L.sub.LP is the parasitic inductance associated with wire 24.sub.L and lead 26.sub.L. (The parasitic inductances associated with lines 16.sub.H and 16.sub.L are much smaller than those associated with composite conductors 24.sub.H /26.sub.H and 24.sub.L /26.sub.L and, for the purpose of the model shown in FIG. 2, can simply be considered parts of inductances L.sub.HP and L.sub.LP.)
A battery 30 provides substantially constant external high and low supply voltages V.sub.HHE and V.sub.LLE on respective external lines 32.sub.H and 32.sub.L that respectively connect to leads 26.sub.H and 26.sub.L. External supply voltages V.sub.HHE and V.sub.LLE (whose difference is the overall power supply voltage) are substantially the steady-state values for internal supply voltages V.sub.HHD and V.sub.LLD. V.sub.LLE is typically ground reference (0 volt). Items L.sub.HE and L.sub.LE are the parasitic inductances respectively associated with external supply lines 32.sub.H and 32.sub.L. Normally, line 32.sub.L consists of a large highly conductive ground plane so that L.sub.LE is very small compared to L.sub.HE.
Responsive to a die input signal V.sub.ID, circuitry elements 28 provide a die output signal V.sub.OD. Die input signal V.sub.ID is supplied on an internal die line which connects to a package conductor having a lead (or pin) 34.sub.I that receives an external input signal V.sub.IE. Die output signal V.sub.OD is similarly provided on an internal die line which connects to a package conductor having a lead (or pin) 34.sub.O that supplies an external output signal V.sub.OE. Items L.sub.IP and L.sub.OP are the parasitic inductances respectively associated with these two package conductors (plus the small parasitic inductances respectively associated with the connecting die lines).
The voltage across an inductor (or inductance) is the inductance value multiplied by the rate of change of current flowing through the inductor. When external input V.sub.IE changes in such a way that circuitry elements 28 cause external output V.sub.OE to change, the V.sub.OE change often causes the currents through composite supply lines 16.sub.H /24.sub.H /26.sub.H /32.sub.H and 16.sub.L /24.sub.L /26.sub.L /32.sub.L to change in a rapid oscillatory manner. The resulting voltages across inductances L.sub.HE, L.sub.HP, L.sub.LP, and L.sub.LE typically produce transient HF variations, conventionally referred to as "ringing", in internal supply voltages V.sub.HHD and V.sub.LLD. For example, see U.S. Pat. No. 4,740,717. In turn, the supply line ringing sometimes causes output V.sub.OE to be produced at an undesired value.
When circuitry elements 28 include an HF amplifier, an even greater problem can occur if the supply line ringing penetrates back to the amplifier input line. As a result of the undesired (parasitic) feedback loop that is so formed, the ringing can cause the amplifier to undergo sustained oscillations. This renders the entire IC inoperative.
One approach that has been taken in the prior art to reduce the ringing in voltages V.sub.HHD and V.sub.LLD is to connect an external capacitor between supply leads 26.sub.H and 26.sub.L. These connections create a passive bypass that can substantially decrease the portion of the supply line ringing due to external inductances L.sub.HE and L.sub.LE. However, this approach does not significantly reduce the portion of the ringing caused by internal inductances L.sub.HP and L.sub.LP.
A more complete technique used in the prior art to inhibit supply line ringing is to provide an on-chip bypass capacitor between internal supply lines 16.sub.H and 16.sub.L. FIG. 3 illustrates this technique in which item C.sub.BP is the bypass capacitor. At high frequency, capacitor C.sub.BP effectively short circuits lines 16.sub.H and 16.sub.L so as to reduce the V.sub.HHD and V.sub.LLD ringing that would otherwise result from internal inductances L.sub.HP and L.sub.LP as well as external inductances L.sub.HE and L.sub.LE. Unfortunately, capacitor C.sub.BP must be very large to be effective. It sometimes occupies more chip area than all the rest of circuitry elements 28 together. This is extremely undesirable where, as is generally the case, minimization of die area is important.
Making capacitor C.sub.BP small creates a significant risk that it will form a parallel resonance with inductances L.sub.HE, L.sub.HP, L.sub.LP, and L.sub.LE. The supply line impedance at the resonant frequency becomes very high and leads to a much enhanced likelihood of circuit oscillations.